Semiconductor devices are widely used in the manufacture of electronic appliances such as personal computers, mobile phones, and digital music players. Semiconductor devices are typically installed as the familiar chip, and mounted on a printed wire board in the appliance. The printed wire board has conductors that are used to provide electrical power to the chip, and to carry the electrical signals between the chips in the appliance and the various input/output devices such as keyboards, displays, and network connections. Electronic appliances like these are very popular. One of the reasons for their popularity is their small size. Many are portable, and even those that are not typically are designed so as not to take up too much room on a shelf or desktop. There is, in fact, continuing market pressure to make these devices even smaller, while at the same time enhancing their capabilities. This poses many challenges for designers.
A semiconductor chip, generally speaking, is a small piece of treated silicon or some other semiconductor material that is encapsulated in the familiar plastic enclosure. A semiconductor material is one that conducts electricity only under certain circumstances, such as the application of a small electrical charge. The small piece of semiconductor material in a chip has fabricated on its surface thousands, or perhaps millions of tiny electrical components that can take advantage of this property to manipulate electrical signals in a way that makes operation of the electronic appliance possible. These electrical components are interconnected to form integrated circuits, and there is provided through bonding wires, leads, or conductive bumps the external connection referred to above.
One such tiny electrical component is a transistor. A transistor is basically a small, solid-state switch. One such device is shown in FIG. 1. FIG. 1 is a side (elevation) view illustrating in cross-section a typical transistor 10. Note that, as with all of the Figures herein, FIG. 1 is not necessarily drawn to scale. Transistor 10 includes a gate structure 20, which in operation is used to control the flow of electricity through the channel region 23 beneath it. The gate structure 20 includes a gate electrode 25, which is separated from the substrate 12 by a dielectric layer 21. The substrate 12, as mentioned above, is often formed of silicon or another suitable material. The dielectric layer 21 may be silicon dioxide that has been formed on the surface of the substrate 12. Spacers 28 and 29 are disposed on either side of the gate structure 20, and may be made, for example, of silicon nitride. A contact region 26 is formed at the top of gate electrode 25 to provide for a reliable external electrical connection. In this example, the gate electrode 25 is formed of a poly (polycrystalline silicon) material, and the contact region 26 of a metal such as copper. Other materials and configurations (not shown) may also be used.
In the example of FIG. 1, a source region 22 and a drain region 24 have been formed in the substrate 12, and together define channel region 23. As alluded to above, electrical current can be induced to flow through channel region 23 if an appropriate voltage is applied to the gate electrode 25. STI (shallow trench isolation) structures 14 and 16 help to prevent undesirable current leakage into other regions of substrate 12. Note that channel current may be considered to be carried by negative (n-type) or positive (p-type) charge carriers. The local nature of the substrate and of the source and drain regions determine which type of carrier will be exploited in a particular transistor. The nature of each region is determined by the type of ion implantation, or doping, used to form it.
Transistors such as transistor 10 illustrated in FIG. 1 are sometimes referred to as MOSFETs (metal-oxide semiconductor field effect transistors—even though poly instead of metal is now often used for the gate electrode). A MOSFET having an n-type or p-type source and drain regions are called, respectively, NMOS and PMOS semiconductor devices. It has been found that NMOS and PMOS devices may be used together to advantage as CMOS (complimentary metal oxide semiconductor) devices. An example is shown in FIG. 2.
FIG. 2 is side view illustrating in cross-section a typical pair of transistors in a CMOS configuration. CMOS semiconductor device 50 includes an NMOS device 60 and a PMOS device 70. In this example, substrate 52 is a p-type substrate. Since the PMOS device 70 requires an n-type substrate, an n-well 53 has been formed in p-type substrate 52 for this purpose. Gate structure 71 has been formed over the n-well 53. Gate structure 71 of PMOS device 70 includes a gate electrode 75 separated from n-well 53 of substrate 52 by a gate dielectric 77. Metal contact 76 is disposed on the poly gate electrode 75. A source 72 and drain 74 have been formed in n-well 53, defining a p-channel 73. Likewise, gate structure 61 has been formed over the p-substrate 52. Gate structure 61 of NMOS device 60 includes a gate electrode 65 separated from substrate 52 by a gate dielectric 67. Metal contact 66 is disposed on the poly gate electrode 65. A source 62 and drain 64 have been formed in substrate 52, defining an n-channel 63. NMOS device 60 and PMOS device 70 are separated by STI 55, and STIs 54 and 56 provide isolation from other devices (not shown) formed on the same substrate 52.
As might be apparent, efficient carrier mobility through the channels 23, 63, and 73 described above is very important. Achieving it, however, becomes more difficult as channel length, along with the dimensions of the various transistor components, are scaled-down to provide the smaller and more capable devices demanded by the market. One way to enhance carrier mobility is to induce a strain in the channel-region material. There are several ways to do this. One is to use as channel-region material a silicon layer on a silicon-germanium base. Another is to use appropriately formed STIs that provide a stress force to induce strain in the channel region. Still another method involves using a stress producing CESL (contact etch stop layer).
The CESL (not shown in FIGS. 1 and 2) is typically formed as a uniform layer over the transistors, such as NMOS device 60 and PMOS device 70, including their respective source and drain regions. The CESL may be formed so as to produce either a tensile or a compressive stress in the channel region. The different devices, however, require different stresses for carrier-mobility enhancement. An NMOS device, for example, benefits from a tensile stress CESL, while a PMOS device benefits from compressive stress. For this reason, fabrication processes have been developed that place a tensile CESL over each NMOS device and a compressive CESL over every PMOS device. Generally speaking, this is achieved by forming structures, for example of photoresist, that protect one or the other of the devices when the appropriate CESL is being formed or selectively removed from those areas where it is not needed. In this way, both NMOS and PMOS devices can benefit from CESL-produced stress.
Unfortunately, a disadvantage of existing methods of CESL formation is that the means for adjusting the channel stress are often limited to changing the overall thickness of the CESL or the pitch at which adjacent semiconductor devices are spaced. Control of channel stress is sometimes inhibited by other factors. Needed, then, is a way to fabricate a stress-inducing CESL for transistors and similar semiconductor devices that is capable of increasing the channel stress in a controllable fashion without the need for significantly-increased CESL thickness. The present invention provides just such a solution.